1. Technical Field
The present disclosure relates to semiconductor processing, and more specifically, to a method of forming a fully self-aligned via using a sidewall image transfer process to define a lateral dimension of the via.
2. Related Art
In the microelectronics industry as well as in other industries involving construction of microscopic structures (e.g., micromachines, magnetoresistive heads, etc.) there is a continued desire to reduce the size of structural features and microelectronic devices and/or to provide a. greater amount of circuitry for a given chip size. Miniaturization in general allows for increased performance (more per clock cycle and less heat generated) at lower power levels and lower cost. Present technology is at atomic level scaling of certain micro-devices such as logic gates, FETs and capacitors, for example. Circuit chips with hundreds of millions of such devices are common.
Sidewall image transfer (SIT), also known as self-aligned double patterning (SADP), is a technique to generate sub-lithographic structures, which aids in the afore-mentioned miniaturization. SIT involves the usage of a sacrificial structure (e.g., a mandrel, typically composed of a polycrystalline silicon or organic material), and a sidewall spacer (such as silicon dioxide or silicon nitride, for example) having a thickness less than that permitted by the current lithographic ground rules formed on the sides of the mandrel (e.g., via oxidization or film deposition and etching). After removal of the mandrel, the remaining sidewall spacer is used as a hard mask (HM) to etch the layer(s) below, for example, with a directional reactive ion etch (RIE). Since the sidewall spacer has a sub-lithographic width (less than lithography allows), the structure formed in the layer below will also have a sub-lithographic width. In SIT processing, the side wall spacer hard mask is either removed during the etching of the underlying layer or removed after the etching.
Circuit chips also include a large number of levels including conductive lines or wires that connect different parts of the chip together. Interconnects couple conductive lines between levels, and are oftentimes referred to as vias or contact vias. One challenge in making interconnects of semiconductor devices in ever-smaller circuit chips is that it is difficult to control the via's width relative to an intended critical dimension (CD). As shown in FIGS. 1 and 2, in widely used ‘self-aligned via’ (SAV) processing, an opening 8 for a via is constructed by patterning a hard mask 10, e.g., of titanium nitride (TiN) and tetraethyl orthosilicate, Si(OC2H5)4)(TEOS), over a dielectric layer 12 overlaying a level 14 such as an interconnect level with dielectric and a wire 16, and etching opening 8 into dielectric layer 12 using hard mask 10. FIG. 1 shows opening 8 in a first cross-sectional direction and FIG. 2 shows opening 8 in a second, perpendicular cross-sectional direction. During etching, as observed by comparing FIGS. 1 and 2, hard mask 10 controls an intended critical dimension (CD) in one direction but not in the other direction. For example, as shown in FIG. 1, opening 8 can be confined in an x-direction, perpendicular to a line to which the via is being coupled in an underlying layer, resulting in critical dimension CDx, but, as shown in FIG. 2, the dimension is unconstrained in a y-direction, parallel to wire 16. That is, the resulting hard mask opening in the y-direction cannot control the y-direction dimensions for the vias (2 shown) etched in that direction. This situation results in an unintended, elongated dimension UDy in hard mask 10 for the two vias.
The above problem of improper via dimensioning during fabrication may be caused by a number of self-aligned via processing characteristics. First and foremost, the critical dimension control in the different directions is not maintained outside of the hard mask. In addition, the aspect ratio control of the self-aligned via may also not be controlled leading to improper dimensions. A number of approaches to solving the above problem employ some form of a double exposure via mask to form a bi-directionally aligned via through the dielectric layer. These approaches suffer from a number of drawbacks such as the need for additional masking layers increasing the overlay placement, the need for more precise etching bias control and tuning to control the hard mask critical dimension, and finally, the lack of control of the via placement on the lower interconnect level.